library ieee;
use ieee.std_logic_1164.all;

entity sum1bit is
port(a,b,Cin:in std_logic;
	 s,Cout:out std_logic);
end sum1bit;

architecture sum of sum1bit is

begin
	s<=Cin xor a xor b;
	Cout<=(a and b) or (Cin and (a or b));
end sum;

